1. Field of the Invention
Generally, the present invention relates to sophisticated integrated circuits, and, more particularly, to methods of forming reverse shallow trench isolation structures with super-steep retrograde wells for use with field effect transistor elements.
2. Description of the Related Art
In modern ultra-high density integrated circuits, device features have been steadily decreasing in size to enhance the performance of the semiconductor device and the overall functionality of the circuit. In addition to an increase in the speed of operation due to reduced signal propagation times, reduced feature sizes allow an increase in the number of functional elements in the circuit in order to extend its functionality. Today, advanced semiconductor devices may include features having critical sizes of 32 nm or even less, and the development of technology nodes based on device critical size dimensions of 22 nm, 14 nm and even smaller is ongoing.
The fabrication of integrated circuits requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently the most common approach, due to the superior characteristics in view of operating speed and/or power consumption. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel (NMOS) transistors and P-channel (PMOS) transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated from the channel by a thin gate insulating layer, or gate dielectric. In operation, an appropriate control voltage is applied to the gate electrode, which thereby forms a conductive channel below the gate electrode.
The conductivity of the channel region depends on several factors, including dopant concentration, the mobility of the charge carriers, and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Of these factors, the channel length is a primary and important contributing factor in overall device speed, and as such, a reduction of the channel length, i.e., the critical size, of transistors has been a major focus in ongoing device development and improvement. However, the continuous shrinkage of the transistor dimensions carries with it a plurality of issues which have to be addressed so as to not unduly offset the advantages that may be obtained by steadily decreasing the channel length of MOS transistors, such as the development of enhanced photolithography and etch strategies necessary to reliably and reproducibly create circuit elements having very small critical dimensions for new device generations.
In most modern semiconductor devices, and in particular, those based on CMOS technology, the various device regions, which often include one or more circuit elements, are electrically separated by electrical isolation structures, sometimes in the form of shallow trench isolation (STI) structures. It should be appreciated that, as the critical sizes of circuit elements decreases, the dimensions of the device regions may also decrease, as well as the critical sizes of the isolation structures separating those device regions, so that the overriding benefits of increased device density may be realized. However, decreasing the critical size of an isolation structure, such as an STI, can sometimes lead to a variety of device processing and reliability issues.
For example, in many device applications, such as those based on a critical size of 32 nm and smaller, the depth of a typical STI often ranges from 200-300 nm, whereas the width is generally on the order of 40-60 nm or even less. Accordingly, the aspect ratio (i.e., the depth-to-width ratio) of the trench opening in which the STI is formed may be at least approximately 6:1, and in some applications may range as high as approximately 10:1. Properly filling such a narrow-gap high aspect ratio trench opening without creating voids can be problematic. Furthermore, the typical gap-fill material deposition processes that are most often used to fill such high aspect ratio openings often form a deposited material that is substantially more susceptible to etch attack during the plurality of etching and cleaning steps to which the device may be exposed during subsequent processing sequences. FIGS. 1A-1F schematically illustrate a conventional prior art integration scheme that has been used for forming shallow trench isolation structures of a semiconductor device wherein one or more of the above-described problems may arise, and which will be described in further detail below.
FIG. 1A schematically illustrates a semiconductor device 100 in very early stage of device manufacture. The semiconductor device 100 includes a substrate 101, which may represent any appropriate carrier material for having formed thereon or thereabove a semiconductor layer 102. In the manufacturing stage shown in FIG. 1A, a thin silicon dioxide material layer 103, sometimes referred to as a pad oxide layer 103, has been formed on the semiconductor layer 102, and a silicon nitride material layer 104, sometimes referred to as a pad nitride layer 104, has been formed on the pad oxide layer 103. Additionally, a resist layer 105 has been formed above the pad nitride layer 104 and patterned using photolithography techniques well known in the art to form openings 105a in the resist layer 105, each of which correspond to respective locations and sizes of the shallow trench isolation (STI) structures that will be formed in the semiconductor layer 102 during succeeding processing steps, as discussed below.
After the openings 105a have been formed in the resist layer 105, a suitable anisotropic etch process 106, such as a reactive ion etch process and the like, is performed using the patterned resist layer 105 as an etch mask, as shown in FIG. 1B. During the etch process 106, the openings 105a are extended through the pad nitride layer 104, through the pad oxide layer 103, and into the semiconductor layer 102, thereby forming the trench openings 102a in the layer 102. In some cases, the depth of the trench openings 102a is established based on the duration of the etch process 106. In other cases, such as where devices are formed on so-called silicon-on-insulator (SOI) substrates, the depth of the trench openings is established based upon the position of a buried insulation layer (not shown) on which the semiconductor layer 102 is formed, which may be used as an etch stop layer during the etch process 106.
Next, as shown in FIG. 1C, the resist layer 105 is removed from above the pad nitride layer 104 and a thermal oxidation process 107 is performed so as to form an oxide liner 108 on the exposed surfaces (i.e., sidewalls and bottom) of each of the trench openings 102a. The oxide liner 108 generally improves the adherence of the subsequently deposited oxide material layer 110 that is used to form each of the STI structures 110i (see, FIGS. 1D-1F).
FIG. 1D schematically illustrates the semiconductor device 100 of FIG. 1C during a subsequent deposition process 109, during which the oxide material layer 110 is formed above the device 100 so as to overfill each of the lined trench openings 102a and cover the pad nitride layer 104. Thereafter, as shown in FIG. 1E, a planarization process 111, such as a chemical mechanical polishing (CMP) process, is performed on the oxide material layer 110 using the pad nitride layer 104 as a CMP stop layer, so that the oxide material layer 110 is removed from above the pad nitride layer 104.
FIG. 1F shows the semiconductor device 100 after a suitable etch process 112, such as a wet etch process based on phosphoric acid and the like, has been performed so as to selectively remove the remaining portions of the pad nitride layer 104, thus forming the STI structures 110i. Furthermore, as shown in FIG. 1F, the STI structures 110i are positioned in the semiconductor layer 102 so as to separate the semiconductor layer 102 into various device active regions, such as the active regions 122A and 122B. Depending on the desired device conductivity in each of the active regions 122A and 122B, specific dopant types may be introduced into the respective active regions 122A and 122B after the STI structures 110i have been formed, or dopants may be present in the semiconductor layer 102 prior to the above-described steps, such that the active regions 122A, 122B form either an n-well (i.e., where PMOS devices are formed) or a p-well (i.e., where NMOS devices are formed).
As noted previously, the aspect ratios of the STI trenches 102a may be relatively high, e.g., greater than about a 6:1 depth-to-width ratio. Accordingly, the deposition process 109 that is used to form the material 110 in each of the trench openings 102a must generally have very good gap-fill capabilities, so that the inclusion of any void regions in the STI structures 110i can be substantially avoided. In some applications, the deposition process 109 is a high density plasma (HDP) oxide deposition process—sometimes referred to as an HDP oxide process—which is a specialized chemical vapor deposition (CVD) process that has been shown to provide relatively good gap-fill capabilities for aspect ratios up to approximately 7:1 and higher. In other applications, such as when the aspect ratio of the trench openings 102a exceeds 8:1 or even 10:1, the deposition process 109 may be a high aspect ratio process (HARP) or enhanced high aspect ratio process (eHARP), which are specialized sub-atmospheric chemical vapor deposition (SACVD) processes based on tetraethyl orthosilicate (TEOS) and ozone.
It should be appreciated that, during subsequent device processing steps, the shallow trench isolation structures 110i may be exposed to various etch and/or cleaning recipes, all of which may potentially attack the oxide material formed in the trench openings 102a using one of the high gap-fill HDP oxide or HARP/eHARP oxide CVD deposition processes. Furthermore, it is well understood that the oxide materials that are deposited using these high-gap fill processes generally exhibit a significantly higher etch rate when exposed to the various wet etch recipes that may be utilized during device processing than does a corresponding thermally grown oxide material. Accordingly, in some applications, the oxide material layer 110 is sometimes exposed to a thermal annealing step prior to performing the planarization process 111 so as to increase the etch resistance of the deposited oxide material 110, a step that is sometimes referred to as a “densification” process. However, while such densification processes may tend to increase the etch resistance of the as-deposited oxide material layer 110 to a greater or lesser degree (for example, depending on the specific process parameters), the resulting wet etch rate of such high gap-fill deposited oxide materials 110 is typically somewhere in the range of approximately 1.5 to 7 times greater than that of a thermal oxide material. Accordingly, some processing defects can occur during later manufacturing stages, as will be further described with respect to FIGS. 1G-1I below.
FIG. 1G is transmission electron microscopy (TEM) photograph showing a representative semiconductor device 170 which utilizes a typical shallow trench isolation structure configuration that is formed using a conventional prior art manufacturing process flow. As shown in FIG. 1G, a typical STI structure 140i—which is typically made up of high gap-fill deposited oxide material such as an HDP oxide or HARP/eHARP oxide—separates and defines two respective active regions 152a and 152b of a semiconductor material layer. Furthermore, in the manufacturing stage shown in FIG. 1G, the semiconductor device 170 has been exposed to at least some additional processing steps after the STI structure 140i was formed, such as cleaning and/or etching steps, and the like. Moreover, the semiconductor device 170 shown in FIG. 1G includes an additional passivation layer 145, which was formed above the device in preparation for the TEM process. The dashed line 146 indicates an interface between the passivation layer 145 and the underlying STI structure 140i, thus highlighting the irregular upper surface contour of the STI structure 140i. 
As noted above, the semiconductor device 170 has been exposed to various cleaning and/or etching steps during device processing, and, due to the increased etch rates typically displayed by the high gap-fill deposited HDP or HARP/eHARP oxide materials, a divot 140d has been formed near an upper corner of the STI structure 140i, which, in the particular device shown, is on the order of approximately 7 nm. As may be appreciated by those of ordinary skill in the art, the presence of the divot 140d in the STI structure 140i can often lead to other processing-related problems. For example, depending on the size and/or depth of the divot 140d, residues that are created during other processing steps, such as cleaning and/or etching steps and the like, can sometimes build up in the divot 140d. Such residues can be difficult to remove, and if left in place, can lead to significant device operating problems, such as short problems or leakage. Additionally, as the size and/or depth of the divot 140d increases during device manufacture, other processing related issues may arise, as will be further discussed with respect to FIG. 1H and FIG. 1I below.
FIG. 1H is a TEM photograph of a representative semiconductor device 180 showing another type of divot defect 140d in an STI structure 140i. As shown in FIG. 1H, the semiconductor device 180 includes a typical gate electrode structure 160 formed above an active region 152a, and a non-functional gate electrode 161 formed above the STI structure 140i. As those of ordinary skill in the art may appreciate, non-functional gate electrode structures, such as the gate electrode structure 161, are sometimes formed above the isolation regions of a semiconductor device so as to provide a substantially uniform device patterning density, which can sometimes help reduce other processing-related deficiencies and/or defects, such as those associated with lithography patterning effects and CMP dishing effects, and the like. Additionally, a strained semiconductor material region 155 has been formed in the area of the source/drain region between the gate electrode structures 160 and 161.
Typically, the strained semiconductor material region 155 is selectively formed using an epitaxial growth process in a cavity (not shown) that is formed in the semiconductor material of the active region 152a between the two gate electrode structures 160, 161. However, due to the relatively higher etch rate associated with the HDP or HARP/eHARP oxide material of the STI structure 140i, a divot 140d (indicated by the dashed line 147) has been formed at the upper corner of the STI structure 140i. Furthermore, since an epitaxial growth process will only form silicon-based materials on the exposed surfaces of other silicon-based materials, the strained semiconductor material region 155 will not be fully formed due to faceting of epitaxially grown materials arising from the divot—, e.g., substantially up to the level of the gate dielectric layer of the gate electrodes 160 and 161—in the source/drain region between the gate electrodes 160 and 161, as shown in FIG. 1H. Furthermore, the presence of the divot 140d may also lead to the processing-related residue issues as previously described above.
FIG. 1I is a TEM photograph of yet another representative semiconductor device 190 that shows a different type of divot-related device defect. As shown in FIG. 1I, two closely spaced gate electrode structures 160 are formed above a common active region 152a of the semiconductor device 190. Additionally, the semiconductor device 190 includes raised source/drain regions 156, which are typically formed adjacent to the sides of the gate electrode structures 160 during an epitaxial growth process. However, FIG. 1I shows a divot-related defect wherein an extended portion 156e of one of the epitaxially formed raised source drain regions 156 has grown down and into a divot 140d that was formed in an upper corner of the STI structure 140i during earlier device processing steps, such as an etch and/or clean sequence and the like. As noted above, such defects can be difficult to remove, or can trap and/or leave behind residues during other processing activities, thus potentially leading to reduced device performance and or product yield.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.